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    Timed SystemC Waiting-State Automata

    Third International Workshop on Verification and Evaluation of Computer and Communication Systems (VECoS 2009)

    Rabat, Morroco, 2 - 3 July 2009


    Nesrine Harrath and Bruno Monsuez


    System-Level Modeling using system-level languages like SystemC or SystemVerilog is gaining more and more popularity. They are supposed to provide the garantee of critical functional properties about the interaction between concurrent processes like determinism or liveness up to a basic unit, the delta-cycle. Additionnally to this functional correctness, system level models should also provide valuable information about important non-functional properties like time constraints. Since timing properties (execution times, delays, periods, etc.) are especially important in performance verification of multiprocessing real-time embedded systems [1], we propose a formal model based on SystemC waiting-state automata [2] that conforms to the SystemC scheduler up to delta-cycles (1) and that also conforms to the provided time constraints (2).


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